ARM EN0-001 問題集

質問 1：
In a hardware system that runs software providing secure systems, which of the following describes the behavior of external memory and peripherals?
A. They are not accessible when the processor is in Non-secure state
B. They cannot know whether the processor is performing a Secure or Non-secure access
C. They are required to give an ERROR response when Secure code accesses Non-secure locations in memory
D. They can use the Secure or Non-secure status of the access to decide what response to give
正解：D

質問 2：
An interrupt handler contains the following instruction sequence at the end. The purpose of these instructions is to clear the interrupt request in the interrupt controller and then safely re-enable interrupts.
STR r0, [r1] ; write to interrupt controller register to clear interrupt request
<x>
CPSIE i ; re-enable IRQ interrupts Which of the following instructions should be placed at position <x> in order to ensure that the interrupt controller sees the write before interrupts are re-enabled?
A. DSB
B. DMB
C. NOP
D. ISB
正解：A

質問 3：
In an ARMv7 processor that includes the Advanced SIMD (NEON) extension, how many single precision floating point values can be stored in the Q0 register?
A. 2
B. 8
C. 4
D. 1
正解：C

質問 4：
Which of the following statements regarding Strongly-ordered memory is architecturally FALSE?
A. A write to Strongly-ordered memory is permitted to complete before it reaches the peripheral or memory component accessed by the write
B. Address locations marked as Strongly-ordered memory are never held in a cache
C. The number and size of accesses to Strongly-ordered memory must be the same as that specified by the program
D. The architecture does not permit speculative data accesses to Strongly-ordered memory
正解：A

質問 5：
If the performance of an application remains unchanged when the core clock speed of a Cortex-A9 processor is reduced, what can you deduce about the system?
A. The processor is NOT the limiting factor on performance
B. The core has stopped carrying out speculative data memory accesses
C. The Clocks Per Instruction (CPI) of the processor has increased
D. Instruction cache utilization has improved
正解：A

質問 6：
The interval of time from an external interrupt request signal being raised to the first fetch of an instruction of the interrupt handler is called the interrupt:
A. Jitter
B. Service thread
C. Priority
D. Latency
正解：D

質問 7：
A simple system comprises of the following memory map:
Flash - 0x0 to 0x7FFF
RAM - 0x10000 to 0X17FFF
When conforming to the ABI, which of the following is a suitable initial value for the stack pointer?
A. Top address of flash (0x8000)
B. Bottom address of RAM (0x10000)
C. Bottom address of flash (0x0000)
D. Top address of RAM (0x18000)
正解：D